1. Field of the Invention
This invention relates to the design of charge pumps, and in particular, to the design of charge pumps in high voltage integrated circuit technology. This invention is also applicable to other integrated circuit technology where low start-up voltage condition is desired.
2. Description of the Prior Art
Charge pumps are circuit elements using the pumping action of diode connected MOSFETs and MOS capacitors to provide a voltage source of higher voltage than the power supplies. The charge pumping effect may be achieved by a MOS capacitor, which is a MOSFET with its source and drain terminals shorted to each other, and with its gate terminal connected to a diode connected MOSFET (known also as a MOSFET diode). A diode connected MOSFET is a MOSFET with its gate and source terminals shorted to each other. By applying an oscillating voltage to the tied source and drain terminals of the MOS capacitor, a successively higher voltage is induced at the source terminal of the MOSFET diode with time, until a steady state voltage is reached.
FIG. 1a shows a two-stage charge pump circuit in the prior art. As shown in FIG. 1a, and throughout the following description, MOS capacitors (e.g. capacitors 120 and 130) are shown to be n-MOSFETs. The use of n-MOSFET in this description is for the purpose of example only. The skilled person in the art will be able to infer from the following description and the accompanying drawings, corresponding circuits using p-MOSFETs.
In FIG. 1a, the source-drain terminal of MOS capacitor 120 is connected to clock input .PHI., the gate terminal of MOS capacitor 120 is connected to node 125, which is connected to the gate and drain terminals of NMOS transistor 110, and the source terminal of NMOS transistor 100. The drain terminal of NMOS transistor 100 is connected to a supply voltage Vpp. The source terminal of NMOS transistor 110 is connected to node 135, which is the the gate terminal of MOS capacitor 130. The gate and drain terminals of NMOS transistor 140 are also connected to node 135. The MOS capacitor 130 is driven at it source-drain terminal by clock input .PHI. , which is the non-overlapping complementary signal to clock signal .PHI. (see FIG. 1b). MOS capacitor 120 and MOSFET diode 110 form the first stage of this charge pump circuit. MOS capacitor 130 and MOSFET diode 140 form the second, and, in this implementation, the output stage of the charge pump circuit. The source terminal of NMOS transistor 140 is tapped as the output terminal V.sub.out of this charge pump circuit.
Initially, through NMOS transistors 160 and 100, node 125 is precharged to within the supply voltage VCC less the threshold voltages (Vt) of NMOS transistors 160 and 100.
FIG. 1b shows the non-overlapping and complementary waveforms of clock inputs .PHI. and .PHI. . When clock input .PHI. is low, MOS capacitor 120 is on. As .PHI. goes high, node 125 is capacitively coupled to a voltage equal to its precharge voltage plus the voltage swing of clock input .PHI., with some loss due to the parasitic capacitance at node 125. This turns on MOSFET diode 110 which charges up node 135. When clock input .PHI. goes low, node 125 follows, thus turning off transistor 110. Immediately thereafter, clock input .PHI. goes high which increases the voltage at node 135 by the voltage swing of clock input .PHI. times a capacitive coupling ratio. The charging of node 135 turns on MOSFET 140 which charges up V.sub.out.
Node 125 is precharged to a higher voltage with each successive clock cycle, until this voltage is equal to either (V.sub.out -Vt) or Vpp, whichever is less, where Vt is the threshold voltage of transistor 100. The maximum output voltage V.sub.out of a stage in the pump is equal to the maximum precharge voltage plus the clock voltage V.sub..PHI. times the coupling ratio K less the Vt of the diode connected MOSFET. Thus, the maximum output voltage of this implementation is: EQU V.sub.out.sup.max =Vpp+2(KV.sub..PHI. -V.sub.t)
where ##EQU1##
C.sub.120 and C.sub.130 are the capacitances of MOS capacitors and 130 respectively; C.sub.STRAY, 125 and C.sub.STRAY, 135 are the parasitic capacitances at nodes 125 and 135 respectively.
A requirement for the initialization of the pumping action is that MOS capacitor 120 must be on; that is, its gate voltage at node 125 must exceed its threshold voltage (Vt). The voltage at node 125 is initially the voltage power supply VCC, less the two threshold voltage drops at transistors 100 and 160. This voltage at node 125 must be greater than the threshold voltage (approximately 0.7 volts) of MOS capacitor 120. Hence, the supply voltage VCC must not fall below 2.1 volts in the worst case.
FIG. 2 shows an application of a charge pump circuit. In FIG. 2, a charge pump circuit 220 is used to modulate node 270 to keep node 260 at constant voltage despite varying current requirements of current source 240 drawing time-varying current I.sub.out. Voltage V.sub.260 at node 260 is held to ##EQU2##
If node 260 falls too low due to increased current demand, the comparator will enable oscillator 210 and pump the gate terminal of transistor 250 higher, so that transistor 250 can supply the required current at its source terminal 260 to maintain Node 260 at the required voltage V.sub.260.
In general, the voltage Vmax attainable by an n-stage charge pump is given by: EQU Vmax=Vpp+n(aV-Vt)
where:
Vt is the threshold voltage of the MOSFET diode; PA1 Vpp is the supply voltage; PA1 V is the voltage swing in the clock input signal .PHI.; PA1 n is the number of stages in the charge pump; and PA1 a is the fraction of the capacitance at the gate terminal of the MOS capacitor to the total capacitance of the capacitor gate node, which includes the parasitic capacitance of the MOSFET diode (such as MOSFET diodes 110 & 140). This fraction is typically less than 1.
The charge pump mechanism may be limited, however, if the desired highest voltage is beyond the oxide breakdown voltage of the MOS capacitor. This is because the voltage difference built up across the gate and drain-source terminals of MOS capacitor 120 or 130 may be large enough to exceed the breakdown voltage of the thin gate oxide in the MOS capacitor before the desirable output voltage is reached. In integrated circuit designs, it is generally desirable to have a thin gate oxide. Therefore, the goal of achieving highest voltage in the charge pump circuit is in conflict with the generally desirable goal of having thin gate oxides. In one application, the desirable voltage to be achieved in the charge pump circuit is 17 volts, but the thin oxide breakdown voltage is around 13 volts. In the prior art, voltage clamping circuit elements are used to avoid breakdown by limiting the voltage drop across the gate and source-drain of the MOS capacitor. While breakdown of the MOS capacitor is avoided by the voltage clamp, the output of the charge pump circuit remains limited by the oxide breakdown voltage of the MOS capacitor.
Therefore, it is an object of the current invention to provide a charge pump circuit capable of attaining a higher voltage output than the oxide breakdown voltage across the gate and source-drain terminals of the MOS capacitor.